SOC Verification Enviorment
Verification Suite created by Akshat Baranwal
Interactive High-Level Diagram of the DUT
Hover over the architectural blocks to explore data paths and interfaces.
System Architecture
Hover over a component to see its details. Verichip features a 16-bit architecture with a robust State Machine.
Coverage Metrics
Industry-standard metrics collected via Synopsys VCS URG.
Line
159 / 159
Toggle
398 / 398
Condition
102 / 107 (Module)
FSM
8 / 8 States/Trans
Verification Test Plans
Comprehensive strategies detailing verification intent and methodology.
State Machine
Coverage Groups
alu_regs
25 Variables, 52 Crosses. Validates all ALU commands across Left/Right register inputs.
inters
4 Variables, 4 Crosses. Validates interrupt generation conditions (int1, int2).
colors
4 Variables, 4 Crosses. State machine progression inputs (gold, maroon).
bus_interface
23 Variables, 30 Crosses. Memory mapped I/O access across all 7 registers.