Unified Coverage Report :: Group :: top_verichip7.verichip7.verichip7_cov::alu_regs

Group : top_verichip7.verichip7.verichip7_cov::alu_regs

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Group : top_verichip7.verichip7.verichip7_cov::alu_regs

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/afs/asu.edu/users/a/b/a/abaranw2/eee598sdm/homework07/verichip7_cov.sv

Summary for Group top_verichip7.verichip7.verichip7_cov::alu_regs

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	25	0	25	100.00
Crosses	52	0	52	100.00

Variables for Group top_verichip7.verichip7.verichip7_cov::alu_regs

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_alu_left	4	0	4	100.00	100	1	1	0
cp_alu_right	4	0	4	100.00	100	1	1	0
cp_cmd	9	0	9	100.00	100	1	1	0
cp_norm_valid	2	0	2	100.00	100	1	1	0
cp_reset_valid	2	0	2	100.00	100	1	1	0
cp_state	4	0	4	100.00	100	1	1	0

Crosses for Group top_verichip7.verichip7.verichip7_cov::alu_regs

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cx_norm_cmd_valid	18	0	18	100.00	100	1	1	0
cx_rest_cmd_valid	18	0	18	100.00	100	1	1	0
cx_alu_lr	16	0	16	100.00	100	1	1	0

Summary for Variable cp_alu_left

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	4	0	4	100.00

User Defined Bins for cp_alu_left

Bins

NAME	COUNT	AT LEAST	STATUS
range[0000:3fff]	2511	1
range[4000:7fff]	166	1
range[8000:bfff]	169	1
range[c000:ffff]	140	1

Summary for Variable cp_alu_right

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	4	0	4	100.00

User Defined Bins for cp_alu_right

Bins

NAME	COUNT	AT LEAST	STATUS
range[0000:3fff]	2619	1
range[4000:7fff]	229	1
range[8000:bfff]	82	1
range[c000:ffff]	56	1

Summary for Variable cp_cmd

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	9	0	9	100.00

User Defined Bins for cp_cmd

Bins

NAME	COUNT	AT LEAST	STATUS
undefined	659	1
shr	55	1
shl	56	1
swa	142	1
mvr	40	1
mvl	64	1
sub	113	1
add	336	1
non	1521	1

Summary for Variable cp_norm_valid

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for cp_norm_valid

Bins

NAME	COUNT	AT LEAST	STATUS
valid	156	1
not_valid	1469	1

Summary for Variable cp_reset_valid

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for cp_reset_valid

Bins

NAME	COUNT	AT LEAST	STATUS
valid	23	1
not_valid	582	1

Summary for Variable cp_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	4	0	4	100.00

User Defined Bins for cp_state

Bins

NAME	COUNT	AT LEAST	STATUS
exp_vio	383	1
error	366	1
normal	1625	1
reset	605	1

Summary for Cross cx_norm_cmd_valid

Samples crossed: cp_cmd cp_norm_valid

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	18	0	18	100.00

Automatically Generated Cross Bins for cx_norm_cmd_valid

Bins

cp_cmd	cp_norm_valid	COUNT	AT LEAST	STATUS
undefined	not_valid	239	1
undefined	valid	45	1
shr	not_valid	40	1
shr	valid	7	1
shl	not_valid	41	1
shl	valid	7	1
swa	not_valid	85	1
swa	valid	21	1
mvr	not_valid	27	1
mvr	valid	5	1
mvl	not_valid	42	1
mvl	valid	7	1
sub	not_valid	71	1
sub	valid	13	1
add	not_valid	257	1
add	valid	48	1
non	not_valid	667	1
non	valid	3	1

Summary for Cross cx_rest_cmd_valid

Samples crossed: cp_cmd cp_reset_valid

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	18	0	18	100.00

Automatically Generated Cross Bins for cx_rest_cmd_valid

Bins

cp_cmd	cp_reset_valid	COUNT	AT LEAST	STATUS
undefined	not_valid	102	1
undefined	valid	13	1
shr	not_valid	7	1
shr	valid	1	1
shl	not_valid	7	1
shl	valid	1	1
swa	not_valid	35	1
swa	valid	1	1
mvr	not_valid	7	1
mvr	valid	1	1
mvl	not_valid	12	1
mvl	valid	3	1
sub	not_valid	7	1
sub	valid	1	1
add	not_valid	7	1
add	valid	1	1
non	not_valid	398	1
non	valid	1	1

Summary for Cross cx_alu_lr

Samples crossed: cp_alu_left cp_alu_right

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	16	0	16	100.00

Automatically Generated Cross Bins for cx_alu_lr

Bins

cp_alu_left	cp_alu_right	COUNT	AT LEAST	STATUS
range[0000:3fff]	range[c000:ffff]	13	1
range[0000:3fff]	range[4000:7fff]	139	1
range[0000:3fff]	range[8000:bfff]	5	1
range[0000:3fff]	range[0000:3fff]	2354	1
range[4000:7fff]	range[c000:ffff]	5	1
range[4000:7fff]	range[4000:7fff]	73	1
range[4000:7fff]	range[8000:bfff]	5	1
range[4000:7fff]	range[0000:3fff]	83	1
range[8000:bfff]	range[c000:ffff]	9	1
range[8000:bfff]	range[4000:7fff]	10	1
range[8000:bfff]	range[0000:3fff]	82	1
range[8000:bfff]	range[8000:bfff]	68	1
range[c000:ffff]	range[c000:ffff]	29	1
range[c000:ffff]	range[4000:7fff]	7	1
range[c000:ffff]	range[8000:bfff]	4	1
range[c000:ffff]	range[0000:3fff]	100	1

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