Group : top_verichip7.verichip7.verichip7_cov::inters
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Group : top_verichip7.verichip7.verichip7_cov::inters
SCOREWEIGHTGOALAT LEASTAUTO BIN MAXPRINT MISSING
100.00 1 100 1 64 64


Source File(s) :
/afs/asu.edu/users/a/b/a/abaranw2/eee598sdm/homework07/verichip7_cov.sv


Summary for Group top_verichip7.verichip7.verichip7_cov::inters

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Variables 4 0 4 100.00
Crosses 4 0 4 100.00


Variables for Group top_verichip7.verichip7.verichip7_cov::inters
VARIABLEEXPECTEDUNCOVEREDCOVEREDPERCENTGOALWEIGHTAT LEASTAUTO BIN MAXCOMMENT
cp_int1 2 0 2 100.00 100 1 1 2
cp_int2 2 0 2 100.00 100 1 1 2


Crosses for Group top_verichip7.verichip7.verichip7_cov::inters
CROSSEXPECTEDUNCOVEREDCOVEREDPERCENTGOALWEIGHTAT LEASTPRINT MISSINGCOMMENT
cx_ints 4 0 4 100.00 100 1 1 0


Summary for Variable cp_int1

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for cp_int1

Bins
NAMECOUNTAT LEASTSTATUS
auto[0] 2639 1
auto[1] 347 1


Summary for Variable cp_int2

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for cp_int2

Bins
NAMECOUNTAT LEASTSTATUS
auto[0] 2773 1
auto[1] 213 1


Summary for Cross cx_ints

Samples crossed: cp_int1 cp_int2
CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENTMISSING
Automatically Generated Cross Bins 4 0 4 100.00


Automatically Generated Cross Bins for cx_ints

Bins
cp_int1cp_int2COUNTAT LEASTSTATUS
auto[0] auto[0] 2491 1
auto[0] auto[1] 148 1
auto[1] auto[0] 282 1
auto[1] auto[1] 65 1

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