Summary for Variable cp_cs

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for cp_cs

Bins

NAME	COUNT	AT LEAST	STATUS
selected	1895	1
not_selected	1092	1

---

Summary for Variable cp_rw

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for cp_rw

Bins

NAME	COUNT	AT LEAST	STATUS
read	1968	1
write	1019	1

---

Summary for Variable cp_bytes

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	4	0	4	100.00

User Defined Bins for cp_bytes

Bins

NAME	COUNT	AT LEAST	STATUS
both	980	1
byte1	29	1
byte0	37	1
neither	1941	1

---

Summary for Variable cp_data_in

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	8	0	8	100.00

User Defined Bins for cp_data_in

Bins

NAME	COUNT	AT LEAST	STATUS
range[0000:1fff]	381	1
range[2000:3fff]	63	1
range[4000:5fff]	131	1
range[6000:7fff]	7	1
range[8000:9fff]	189	1
range[a000:bfff]	84	1
range[c000:dfff]	1	1
range[e000:ffff]	107	1

---

Summary for Variable cp_address

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	7	0	7	100.00

User Defined Bins for cp_address

Bins

NAME	COUNT	AT LEAST	STATUS
alu	225	1
rgt	342	1
lft	343	1
con	160	1
cmd	301	1
sta	345	1
ver	95	1

---

Summary for Cross cx_cs_rw_be

Samples crossed: cp_cs cp_rw cp_bytes

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	16	0	16	100.00

Automatically Generated Cross Bins for cx_cs_rw_be

Bins

cp_cs	cp_rw	cp_bytes	COUNT	AT LEAST	STATUS
selected	read	both	7	1
selected	read	byte1	7	1
selected	read	byte0	7	1
selected	read	neither	911	1
selected	write	byte1	8	1
selected	write	both	931	1
selected	write	byte0	16	1
selected	write	neither	8	1
not_selected	read	both	7	1
not_selected	read	byte1	7	1
not_selected	read	byte0	7	1
not_selected	read	neither	1015	1
not_selected	write	byte1	7	1
not_selected	write	both	35	1
not_selected	write	byte0	7	1
not_selected	write	neither	7	1

---

Summary for Cross cx_cs_rw_add

Samples crossed: cp_cs cp_rw cp_address

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	14	0	14	100.00

Automatically Generated Cross Bins for cx_cs_rw_add

Element holes

cp_cs	cp_rw	cp_address	COUNT	AT LEAST	NUMBER	STATUS
[not_selected]	*	*	--	--	14	Excluded

Covered bins

cp_cs	cp_rw	cp_address	COUNT	AT LEAST	STATUS
selected	read	con	53	1
selected	read	ver	53	1
selected	read	sta	250	1
selected	read	lft	156	1
selected	read	cmd	53	1
selected	read	alu	183	1
selected	read	rgt	156	1
selected	write	ver	42	1
selected	write	sta	95	1
selected	write	con	107	1
selected	write	lft	187	1
selected	write	alu	42	1
selected	write	cmd	248	1
selected	write	rgt	186	1